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Rev 0; 1/05
DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM
General Description
The DS2065W is a 8Mb reflowable nonvolatile (NV) SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in a surface-mount module with a 256-ball BGA footprint. Whenever VCC is applied to the module, it recharges the ML battery, powers the SRAM from the external power source, and allows the contents of the SRAM to be modified. When VCC is powered down or out-of-tolerance, the controller write-protects the SRAM's contents and powers the SRAM from the battery. The DS2065W also contains a power-supply monitor output, RST, which can be used as a CPU supervisor for a microprocessor. 27mm2
Features
Single-Piece, Reflowable, PBGA Package Footprint Internal ML Battery and Charger Unconditionally Write-Protects SRAM when VCC is Out-of-Tolerance Automatically Switches to Battery Supply when VCC Power Failures Occur Internal Power-Supply Monitor Detects Power Fail Below Nominal VCC (3.3V) Reset Output can be Used as a CPU Supervisor for a Microprocessor Industrial Temperature Range (-40C to +85C) UL Recognized
DS2065W
Applications
RAID Systems and Servers Industrial Controllers Data-Acquisition Systems Gaming POS Terminals Routers/Switches Fire Alarms PLC
Pin Configuration appears at end of data sheet.
Ordering Information
PART DS2065W-100 TEMP RANGE -40C to +85C PIN-PACKAGE 256 Ball 27mm2 BGA Module SPEED (ns) 100 SUPPLY TOLERANCE (%) 3.3V 0.3V
Typical Operating Circuit
(CE) (WR) (RD)
CE WE OE
DS2065W MICROPROCESSOR OR DSP
DATA
1024k x 8 NV SRAM
8 BITS DQ0-7
ADDRESS
20 BITS
A0-19
(INT)
RST
______________________________________________ Maxim Integrated Products
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DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM DS2065W
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground .................-0.3V to +4.6V Operating Temperature Range ...........................-40C to +85C Storage Temperature Range ...............................-40C to +85C Soldering Temperature...................See IPC/JEDEC J-STD-020C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C.)
PARAMETER Supply Voltage Input Logic 1 Input Logic 0 SYMBOL VCC VIH VIL CONDITIONS MIN 3.0 2.2 0 TYP 3.3 MAX 3.6 VCC 0.4 UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V 0.3V, TA = -40C to +85C.)
PARAMETER Input Leakage Current I/O Leakage Current Output-Current High Output-Current Low Output-Current Low RST Standby Current Operating Current Write-Protection Voltage SYMBOL IIL IIO IOH IOL IOL RST ICCS1 ICCS2 ICCO1 VTP CE = VCC At 2.4V At 0.4V At 0.4V (Note 1) CE = 2.2V CE = VCC - 0.2V tRC = 200ns, outputs open 2.8 2.9 CONDITIONS MIN -1.0 -1.0 -1.0 2.0 10.0 0.5 0.2 7 5 50 3.0 TYP MAX +1.0 +1.0 UNITS A A mA mA mA mA mA V
CAPACITANCE
(TA = +25C.)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN COUT Not tested Not tested CONDITIONS MIN TYP 7 7 MAX UNITS pF pF
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DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V 0.3V, TA = -40C to +85C.)
PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High Impedance from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Impedance from WE Output Active from WE Data Setup Time Data Hold Time SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2 (Note 4) (Note 5) (Note 2) (Note 2) (Note 6) (Note 4) (Note 5) 5 40 0 20 (Note 3) (Note 2) (Note 2) 5 100 75 0 5 20 35 5 35 CONDITIONS MIN 100 100 50 100 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DS2065W
POWER-DOWN/POWER-UP TIMING
(TA = -40C to +85C.)
PARAMETER VCC Fail Detect to CE and WE Inactive VCC Slew from VTP to 0V VCC Slew from 0V to VTP VCC Valid to CE and WE Inactive VCC Valid to End of Write Protection VCC Fail Detect to RST Active VCC Valid to RST Inactive SYMBOL tPD tF tR tPU tREC tRPD tRPU (Note 1) (Note 1) 225 350 CONDITIONS (Note 7) 150 150 2 125 3.0 525 MIN TYP MAX 1.5 UNITS s s s ms ms s ms
DATA RETENTION
(TA = +25C.)
PARAMETER Expected Data-Retention Time (Per Charge) SYMBOL tDR CONDITIONS (Note 8) MIN 2 TYP 3 MAX UNITS years
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DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM DS2065W
Read Cycle
tRC VIH VIL VIH VIL tOH tACC VIH CE VIL tCO VIH VIH VIL
ADDRESSES
tOD VIH OE tCOE tCOE DOUT VOH VOL OUTPUT DATA VALID VIL tOD VOH VOL tOE VIH
(SEE NOTE 9.)
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DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM
Write Cycle 1
DS2065W
tWC ADDRESSES VIH VIL tAW CE VIL tWP WE VIH tODW DOUT HIGH IMPEDANCE tDS VIH DIN VIL (SEE NOTES 2, 3, 4, 6, 10-13.) DATA IN STABLE VIL tDH1 VIH VIL VIL VIH tOEW VIL tWR1 VIH VIL VIH VIL
Write Cycle 2
tWC
ADDRESSES
VIH VIL tAW tWP VIH VIL VIL VIL tWR2
VIH VIL
VIH VIL
CE
VIH
WE tCOE
VIL tODW
VIL
DOUT tDS VIH DIN VIL (SEE NOTES 2, 3, 5, 6, 10-13.) DATA IN STABLE VIL tDH2 VIH
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DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM DS2065W
Power-Down/Power-Up Condition
VCC VTP tDR
~2.5V
tF tPD CE, WE tPU VIH tR tREC SLEWS WITH VCC
BACKUP CURRENT SUPPLIED FROM LITHIUM BATTERY tRPD RST VOL VOL tRPU
(SEE NOTES 1, 7.)
Note 1: RST is an open-drain output and cannot source current. An external pullup resistor should be connected to this pin to realize a logic-high level. Note 2: These parameters are sampled with a 5pF load and are not 100% tested. Note 3: tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. Note 4: tWR1 and tDH1 are measured from WE going high. Note 5: tWR2 and tDH2 are measured from CE going high. Note 6: tDS is measured from the earlier of CE or WE going high. Note 7: In a power-down condition, the voltage on any pin cannot exceed the voltage on VCC. Note 8: The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. Minimum expected data-retention time is based on a maximum of two +230C convection solder reflow exposures, followed by a fully charged cell. Full charge occurs with the initial application of VCC for a minimum of 96 hours. This parameter is assured by component selection, process control, and design. It is not measured directly in production testing. Note 9: WE is high for a read cycle. Note 10: OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. Note 11: If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a highimpedance state during this period. Note 12: If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a highimpedance state during this period. Note 13: If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. Note 14: DS2065W BGA modules are recognized by Underwriters Laboratory (UL) under file E99151.
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DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM DS2065W
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. OPERATING FREQUENCY
DS2065W toc01
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS2065W toc02
BATTERY CHARGER CURRENT vs. BATTERY VOLTAGE
BATTERY CHARGER CURRENT, ICHRG (mA) 7 6 5 4 3 2 1 0 VCHRG = 2.86V 0 0.2 0.4 0.6 0.8 1.0 VCC = CE = 3.3V
DS2065W toc03
7 6 SUPPLY CURRENT (mA) 5 4 3 2 1 0 3.0 3.1 3.2 3.3 VCC (V) 3.4 3.5 1MHz ADDRESSACTIVATED 100% DUTY CYCLE 1MHz CE-ACTIVATED 50% DUTY CYCLE TA = +25C 5MHz CE-ACTIVATED 50% DUTY CYCLE 5MHz ADDRESS-ACTIVATED 100% DUTY CYCLE
200 190 SUPPLY CURRENT (A) 180 170 160 150 140 VCC = CE = 3.3V VBAT = VCHRG
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3.6
3.0
3.1
3.2
3.3 VCC (V)
3.4
3.5
3.6
DELTA BELOW VCHRG (V)
VCHRG PERCENT CHANGE vs. TEMPERATURE
VCHRG PERCENT CHANGE FROM +25C (%)
DS2065W toc04
VTP vs. TEMPERATURE
DS2065W toc05
DQ OUTPUT-VOLTAGE HIGH vs. DQ OUTPUT-CURRENT HIGH
VCC = 3.3V 3.3
DS2065W toc06
1.0 VCC = 3.3V VBAT = VCHRG 0.5
3.00
3.5
WRITE-PROTECT, VTP (V)
2.95 VOH (V) -40 -15 10 35 60 85
3.1
0
2.90
2.9 2.85 2.7
-0.5
-1.0 -40 -15 10 35 60 85 TEMPERATURE (C)
2.80 TEMPERATURE (C)
2.6 -5 -4 -3 -2 -1 0 IOH (mA)
DQ OUTPUT-VOLTAGE LOW vs. DQ OUTPUT-CURRENT LOW
DS2065W toc07
RST OUTPUT-VOLTAGE LOW vs. OUTPUT-CURRENT LOW
DS2065W toc08
RST VOLTAGE vs. VCC DURING POWER-UP
RST VOLTAGE W/PULLUP RESISTOR (V) TA = +25C 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
DS2065W toc09
0.4 VCC = 3.3V 0.3
0.6 VCC = 2.8V 0.5 0.4
4.0
VOL (V)
0.2
VOL (V) 0 1 2 IOL (mA) 3 4 5
0.3 0.2
0.1 0.1 0 0 0 5 10 IOL (mA) 15 20
VCC POWER-UP (V)
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DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM DS2065W
Pin Description
BALLS A1, A2, A3, A4 B1, B2, B3, B4 C1, C2, C3, C4 D1, D2, D3, D4 E1, E2, E3, E4 F1, F2, F3, F4 G1, G2, G3, G4 H1, H2, H3, H4 J1, J2, J3, J4 K1, K2, K3, K4 L1, L2, L3, L4 M1, M2, M3, M4 N1, N2, N3, N4 P1, P2, P3, P4 R1, R2, R3, R4 T1, T2, T3, T4 U1, U2, U3, U4 V1, V2, V3, V4 W1, W2, W3, W4 Y1, Y2, Y3, Y4 A17, A18, A19, A20 B17, B18, B19, B20 C17, C18, C19, C20 D17, D18, D19, D20 E17, E18, E19, E20 F17, F18, F19, F20 G17, G18, G19, G20 H17, H18, H19, H20 J17, J18, J19, J20 K17, K18, K19, K20 L17, L18, L19, L20 M17, M18, M19, M20 NAME GND N.C. A15 A16 RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND GND GND GND A18 A17 A14 A13 A12 A11 A10 A9 A8 A7 A6 DESCRIPTION Ground No Connection Address Input 15 Address Input 16 Open-Drain Reset Output Supply Voltage Write-Enable Input Output-Enable Input Chip-Enable Input Data Input/Output 7 Data Input/Output 6 Data Input/Output 5 Data Input/Output 4 Data Input/Output 3 Data Input/Output 2 Data Input/Output 1 Data Input/Output 0 Ground Ground Ground Ground Address Input 18 Address Input 17 Address Input 14 Address Input 13 Address Input 12 Address Input 11 Address Input 10 Address Input 9 Address Input 8 Address Input 7 Address Input 6 BALLS N17, N18, N19, N20 P17, P18, P19, P20 R17, R18, R19, R20 T17, T18, T19, T20 U17, U18, U19, U20 V17, V18, V19, V20 W17, W18, W19, W20 Y17, Y18, Y19, Y20 A5, B5, C5, D5 A6, B6, C6, D6 A7, B7, C7, D7 A8, B8, C8, D8 A9, B9, C9, D9 A10, B10, C10, D10 A11, B11, C11, D11 A12, B12, C12, D12 A13, B13, C13, D13 A14, B14, C14, D14 A15, B15, C15, D15 A16, B16, C16, D16 U5, V5, W5, Y5 U6, V6, W6, Y6 U7, V7, W7, Y7 U8, V8, W8, Y8 U9, V9, W9, Y9 U10, V10, W10, Y10 U11, V11, W11, Y11 U12, V12, W12, Y12 U13, V13, W13, Y13 U14, V14, W14, Y14 U15, V15, W15, Y15 U16, V16, W16, Y16 NAME A5 A4 A3 A2 A1 A0 GND GND N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. A19 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. DESCRIPTION Address Input 5 Address Input 4 Address Input 3 Address Input 2 Address Input 1 Address Input 0 Ground Ground No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection Address Input 19 No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection No Connection
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DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM
Functional Diagram
CE DELAY TIMING CIRCUITRY RST
DS2065W
VTP REF
CHARGER CURRENT-LIMITING RESISTOR
UNINTERRUPTED POWER SUPPLY FOR THE SRAM
VCC
VCC CE VSW REF OE WE SRAM DQ0-7
REDUNDANT LOGIC
ML GND
CURRENT-LIMITING RESISTOR
REDUNDANT SERIES FET
BATTERY-CHARGING/SHORTING PROTECTION CIRCUITRY (UL RECOGNIZED)
OE WE A0-A19
DS2065W
Detailed Description
The DS2065W is a 8Mb (1024kb x 8 bits) fully static, NV memory similar in function and organization to the DS1265W NV SRAM, but containing a rechargeable ML battery. The DS2065W NV SRAM constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. There is no limit to the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. This device can be used in place of SRAM, EEPROM, or flash components.
The DS2065W assembly consists of a low-power SRAM, an ML battery, and an NV controller with a battery charger, integrated on a standard 256-ball, 27mm2 BGA substrate. Unlike other surface-mount NV memory modules that require the battery to be removable for soldering, the internal ML battery can tolerate exposure to convection reflow soldering temperatures allowing this single-piece component to be handled with standard BGA assembly techniques. The DS2065W also contains a power-supply monitor output, RST, which can be used as a CPU supervisor for a microprocessor.
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DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM DS2065W
Memory Operation Truth Table
WE 1 1 0 X CE 0 0 0 1 OE 0 1 X X MODE Read Read Write Standby ICC Active Active Active Standby OUTPUTS Active High Impedance High Impedance High Impedance
X = Don't care.
Read Mode
The DS2065W executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) is active (low). The unique address specified by the 20 address inputs (A0 to A19) defines which of the 1,048,576 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (access time) after the last address input signal is stable, providing that CE and OE (output enable) access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE for OE, rather than address access.
energy source to the RAM to retain data. During powerup, when VCC rises above VSW, the power-switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds V TP for a minimum duration of tREC.
Battery Charging
When VCC is greater than VTP, an internal regulator charges the battery. The UL-approved charger circuit includes short-circuit protection and a temperature-stabilized voltage reference for on-demand charging of the internal battery. Typical data-retention expectations of 3 years per charge cycle are achievable. A maximum of 96 hours of charging time is required to fully charge a depleted battery.
Write Mode
The DS2065W executes a write cycle whenever the CE and WE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers have been enabled (CE and OE active) then WE will disable the outputs in tODW from its falling edge.
System Power Monitoring
When the external VCC supply falls below the selected out-of-tolerance trip point, the output RST is forced active (low). Once active, the RST is held active until the VCC supply has fallen below that of the internal battery. On power-up, the RST output is held active until the external supply is greater than the selected trip point and one reset timeout period (tRPU) has elapsed. This is sufficiently longer than tREC to ensure that the SRAM is ready for access by the microprocessor.
Freshness Seal and Shipping
The DS2065W is shipped from Dallas Semiconductor with the lithium battery electrically disconnected, guaranteeing that no battery capacity has been consumed during transit or storage. As shipped, the lithium battery is ~60% charged, and no preassembly charging operations should be attempted. When VCC is first applied at a level greater than VTP, the lithium battery is enabled for backup operation. A 96 hour initial battery charge time is recommended for new system installations.
Data-Retention Mode
The DS2065W provides full functional capability for VCC greater than 3.0V and write-protects by 2.8V. Data is maintained in the absence of VCC without additional support circuitry. The NV static RAM constantly monitors V CC. Should the supply voltage decay, the NV SRAM automatically write-protects itself. All inputs become "don't care", and all data outputs become high impedance. As V CC falls below approximately 2.5V (VSW), the power-switching circuit connects the lithium
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DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM
Recommended Reflow Temperature Profile
PROFILE FEATURE Average ramp-up rate (TL to TP) Preheat - Temperature min (TSmin) - Temperature max (TSmax) - Time (min to max) (ts) TSmax to TL - Ramp-up rate Time maintained above: - Temperature (TL) - Time (tL) Peak temperature (TP) Time within 5C of actual peak temperature (TP) Ramp-down rate Time 25C to peak temperature 183C 60 to 150 seconds 225 +0/-5C 10 to 30 seconds 6C/second max 6 minutes max Sn-Pb EUTECTIC ASSEMBLY 3C/second max
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS2065W, decouple the power supply with a 0.1F capacitor. Use a high-quality, ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, while ceramic capacitors have adequately high frequency response for decoupling applications.
DS2065W
100C 150C 60 to 120 seconds
Using the Open-Drain RST Output
The RST output is open drain, and therefore requires a pullup resistor to realize a high logic output level. Pullup resistor values between 1k and 10k are typical.
Battery Charging/Lifetime
The DS2065W charges an ML battery to maximum capacity in approximately 96 hours of operation when VCC is greater than VTP. Once the battery is charged, its lifetime depends primarily on the VCC duty cycle. The DS2065W can maintain data from a single, initial charge for up to 3 years. Once recharged, this deepdischarge cycle can be repeated up to 20 times, producing a worst-case service life of 60 years. More typical duty cycles are of shorter duration, enabling the DS2065W to be charged hundreds of times, therefore extending the service life well beyond 60 years.
Note: All temperatures refer to top side of the package, measured on the package body surface.
Recommended Cleaning Procedures
The DS2065W may be cleaned using aqueous-based cleaning solutions. No special precautions are needed when cleaning boards containing a DS2065W module. Removal of the topside label violates the environmental integrity of the package and voids the warranty of the product.
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DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM DS2065W
Pin Configuration
TOP VIEW
A B C D E F G H J K L M N P R T U V W Y 1 1 2 GND N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. A19 N.C. A15 A16 RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND GND GND 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 GND A18 A17 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 N.C. N.C. GND GND 1 9 2 0 2 0 A B C D E F G H J K L M N P R T U V W Y
DS2065W
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.

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